Apparatus and method for multilevel coding (MLC) with binary alphabet polar codes

ABSTRACT

A method includes receiving multiple bits to be transmitted. The method also includes applying a first binary alphabet polar code to a first subset of the multiple bits to generate first encoded bits. The first encoded bits are associated with a first bit level of a multilevel coding scheme. The method further includes generating one or more symbols using the first encoded bits and bits associated with a second bit level of the multilevel coding scheme. The first binary alphabet polar code is associated with a first coding rate. In addition, the method could include applying a second binary alphabet polar code to a second subset of the multiple bits to generate second encoded bits. The second encoded bits are associated with the second bit level. The second binary alphabet polar code is associated with a second coding rate such that the bit levels have substantially equal error rates.

CROSS-REFERENCE TO RELATED APPLICATION AND PRIORITY CLAIM

This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 61/885,351 filed on Oct. 1, 2013. This provisional patent application is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

This disclosure is generally directed to communication systems. More specifically, this disclosure is directed to an apparatus and method for multilevel coding (MLC) with binary alphabet polar codes.

BACKGROUND

Many modern wireless and other communication systems encode digital data for transmission over communication paths. One type of coding mechanism involves the use of polar codes, which are used to encode data bits into encoded data bits that are then mapped into symbols for transmission. Polar codes can be used to achieve capacity of binary-input memoryless symmetric channels, meaning the polar codes allow the full capacity of a channel to be utilized. Polar codes allow this to be achieved using low-complexity encoding and decoding algorithms.

Recently, various attempts have been made to use communication channels more efficiently based on higher-order modulation techniques, such as M-ary quadrature amplitude modulation (M-QAM). The phrase “M-ary” modulation generally refers to modulation where there are M constellation points so that one symbol carries log₂(M) bits.

Extending the use of polar codes to systems that use higher-order modulation techniques is not a simple task. For example, output bits from a binary polar code often experience different effective channels because of their mapping to higher-order symbols. As a result, standard techniques for polar code design are not generally applicable to systems using higher-order modulation techniques.

SUMMARY

This disclosure provides an apparatus and method for multilevel coding (MLC) with binary alphabet polar codes.

In a first embodiment, a method includes receiving multiple bits to be transmitted. The method also includes applying a first binary alphabet polar code to a first subset of the multiple bits to generate first encoded bits. The first encoded bits are associated with a first bit level of a multilevel coding scheme. The method further includes generating one or more symbols using the first encoded bits and bits associated with a second bit level of the multilevel coding scheme. The first binary alphabet polar code is associated with a first coding rate.

In a second embodiment, a first encoder is configured to (i) receive multiple bits to be transmitted and (ii) apply a first binary alphabet polar code to a first subset of the multiple bits to generate first encoded bits. The first encoded bits are associated with a first bit level of a multilevel coding scheme. The apparatus also includes a symbol generator configured to map the first encoded bits and bits associated with a second bit level of the multilevel coding scheme to one or more symbols for transmission. The first binary alphabet polar code is associated with a first coding rate.

In a third embodiment, a method includes applying a first binary alphabet polar code to first decoding information associated with one or more symbols to generate first decoded bits. The first decoding information is associated with a first bit level of a multilevel coding scheme. The method also includes outputting the first decoded bits and bits associated with a second bit level of the multilevel coding scheme. The first binary alphabet polar code is associated with a first coding rate.

In a fourth embodiment, an apparatus includes a first decoder configured to apply a first binary alphabet polar code to first decoding information associated with one or more symbols to generate first decoded bits. The first decoding information is associated with a first bit level of a multilevel coding scheme, and the multilevel coding scheme has a second bit level. The first binary alphabet polar code is associated with a first coding rate.

In a fifth embodiment, a method includes identifying a target error rate associated with a multilevel coding scheme, where the multilevel coding scheme has multiple bit levels. The method also includes identifying an effective signal-to-noise ratio (SNR) at each of the bit levels, where the effective SNR is based on a symbol mapping rule used to map bits into symbols. The method further includes identifying a code rate at each bit level using the target error rate and the SNR at that bit level. In addition, the method includes selecting, at one or more of the bit levels, at least one polar code having at least one of the identified code rates so that an overall error rate of each bit level is substantially equal.

Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of this disclosure and its features, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which:

FIGS. 1A and 1B illustrate example systems that use multilevel coding (MLC) with binary alphabet polar codes in accordance with this disclosure;

FIGS. 2 through 7 illustrate example encoding and decoding schemes supporting MLC with binary alphabet polar codes in accordance with this disclosure;

FIGS. 8A and 8B illustrate example methods for using MLC with binary alphabet polar codes in accordance with this disclosure;

FIG. 9 illustrates an example method for designing an MLC coding scheme with binary alphabet polar codes in accordance with this disclosure; and

FIG. 10 illustrates an example device supporting the design of an MLC coding scheme with binary alphabet polar codes in accordance with this disclosure.

DETAILED DESCRIPTION

FIGS. 1A through 10, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitable manner and in any type of suitably arranged device or system.

FIGS. 1A and 1B illustrate example systems that use multilevel coding (MLC) with binary alphabet polar codes in accordance with this disclosure. The systems shown in FIGS. 1A and 1B are for illustration only. The techniques described in this patent document could be used to support wireless or other communications that use MLC with higher-order modulation (such as M-ary quadrature amplitude modulation) and binary alphabet polar codes between or with any suitable devices or systems.

As shown in FIG. 1A, a system 100 includes base stations 102-104. Each base station 102-104 shown in FIG. 1A generally denotes an infrastructure component that provides wireless service to one or more wireless devices. Other types of infrastructure components that are encompassed by the phrase “base station” include enhanced Node Bs (eNBs) and access points. Similarly, a base station can communicate with any number of wireless devices, each of which generally denotes a device that receives wireless service from at least one infrastructure component. Other types of devices that are encompassed by the phrase “wireless device” include mobile stations, user equipment, wireless terminals, or other fixed or mobile devices. The base stations 102-104 could communicate using any suitable protocol(s) supporting the use of polar codes.

As shown in FIG. 1A, each base station 102-104 includes at least one processing device 106 and at least one memory 108. The at least one processing device 106 executes logic in order to control the overall operation of the base station 102-104 and to support communications with wireless devices. The exact operations of the processing device(s) 106 can vary depending on, for example, the protocol(s) supported by the base stations 102-104. Each processing device 106 includes any suitable processing or control device, such as a microprocessor, microcontroller, digital signal processor (DSP), field programmable gate array (FPGA), application specific integrated circuit (ASIC), or discrete logic devices. The at least one memory 108 stores instructions and data used, generated, or collected by the base station 102-104. Each memory 108 includes any suitable volatile or non-volatile storage and retrieval device, such as a random access memory (RAM) or a Flash or other read-only memory (ROM).

Each base station 102-104 also includes multiple communication transceivers 110 a-110 n, each of which (if implemented to support wireless communications) may be coupled to at least one of multiple antennas 112 a-112 n. Each communication transceiver 110 a-110 n supports communications with other devices, such as portable or other wireless devices. Each communication transceiver 110 a-110 n includes any suitable structure supporting communications over one or more wired or wireless communication channels. For example, each communication transceiver 110 a-110 n can include transmit circuitry that facilitates the transmission of signals from the communication transceiver and receive circuitry that facilitates the processing of signals received by the communication transceiver. Each antenna 112 a-112 n represents any suitable structure for transmitting and receiving communication signals, such as a radio frequency (RF) antenna. Note that while each communication transceiver 110 a-110 n is shown here as having its own antenna 112 a-112 n, multiple communication transceivers could share one or more common antennas, or each communication transceiver could have multiple antennas.

A backhaul interface 114 supports communications between the base stations 102-104 themselves or between a base station 102-104 and other component(s) via a backhaul network. For example, the backhaul interface 114 could allow the base stations 102-104 to communicate with one another. The backhaul interface 114 includes any suitable structure for facilitating communications over a backhaul network, such as a microwave communications unit or an optical fiber interface.

FIG. 1B illustrates an example system having a point-to-point transmitter 150 and receiver 160. The transmitter 150 and the receiver 160 could be used in the base stations 102-104 of FIG. 1A (such as in or with the processors 106, communication transceivers 110 a-110 n, or backhaul interfaces 114) or in any other suitable devices. As shown in FIG. 1B, the transmitter 150 includes a forward error correction (FEC) encoder 152, a symbol mapper 154, an analog front end 156, and at least one antenna 158. The FEC encoder 152 receives information bits and generates encoded bits, such as by using MLC with binary alphabet polar codes as described below. The symbol mapper 154 maps the encoded bits into transmit symbols, which the analog front end 156 transmits wirelessly via the antenna(s) 158.

The receiver 160 includes at least one antenna 162, an analog front end 164, an equalizer 166, a symbol demapper or soft slicer 168, and an FEC decoder 170. The analog front end 164 receives symbols transmitted from the transmitter 150 via the antenna(s) 162 and provides the received symbols to the equalizer 166. The equalizer 166 pre-processes the received symbols, and the equalized symbols are used to generate log-likelihood ratio (LLR) values by the symbol demapper or soft slicer 168. The LLR values are used by the FEC decoder 170 to generate decoded information bits. Ideally, the decoded information bits from the FEC decoder 170 match the information bits provided to the FEC encoder 152.

Communications from a transmitter to a receiver can occur using various modulation techniques, such as binary modulation or M-QAM. Higher-order modulation techniques are often desirable because they allow systems to achieve very high levels of spectral efficiency. However, as noted above, standard techniques for polar code design are not generally applicable to systems using higher-order modulation techniques.

This disclosure describes techniques that support the use of MLC with binary alphabet polar codes, including for use in systems that use higher-order modulation techniques such as M-ary QAM. The design of a specific polar code is equivalent to determining a set of “frozen bits” in an input vector. A “frozen bit” denotes a bit whose value is fixed in both the input vector to a polar encoder and in an output vector from a polar decoder. The remaining bits in the input and output vectors are called “information bits” and can be used to transport data over a wireless or other channel.

Some conventional approaches use a set of information bits and frozen bits obtained from Monte Carlo simulations that are run for binary input polar codes or that are optimized for cases when a binary erasure channel (BEC) is used. Early work in polar code design focused on binary channels where the outputs of an encoder are subject to the same binary input channel, meaning bits at the output of the encoder experience the same channel before a decoder. Extending polar codes to higher-order constellations may be necessary for deployment in practical communication systems, which usually use higher-order modulation for better spectral efficiency. Further, binary codes are usually used in practice, and the mapping to higher-order constellations is typically done after the encoder (rather than using non-binary codes). Although the capacity-achieving property of polar codes has been extended to M-ary input alphabets, the combination of (i) binary polar codes and higher-order modulations and (ii) specific designs for QAM modulations in the presence of additive white Gaussian noise (AWGN) has not been fully investigated. The main difficulty in this case is that the output bits from a binary polar encoder experience different effective channels because of their mapping to higher-order symbols. Therefore, standard techniques for polar code design in general are not applicable.

As described in more detail below, this patent document enables the use of binary polar codes with higher-order modulations. A multilevel coding approach uses one or more binary alphabet polar codes (each possibly with a different code parameter or configuration such as code rate or frozen bit locations) with one or more wireless or other communication channels, such as one or more AWGN channels. For example, with a special symbol mapping rule (such as those shown in FIGS. 2, 4, and 6 described below), one or more channels can be partitioned into m bit levels (also called “bit channels”), which are typically identified based on the bit position of the symbol word (symbol mapper input). Different bit levels have different signal-to-noise ratio (SNR) properties. The bits in each bit level experience the same communication channel with the same effective SNR, so the code design problem is reduced to the design of one or more binary codes with suitable code rate(s). The rate of a polar code for a particular bit channel can be selected using knowledge of the Euclidian distance for a bit level in a corresponding multilevel pulse amplitude modulation (M-PAM) scheme, assuming bits in lower bit levels are decoded correctly and known. Thus, the overall error rate (such as the bit error rate or “BER”) for a polar code is substantially characterized or determined by the required rate of the code at a given channel SNR.

Moreover, polarization parameters obtained for true equivalent bit channels can be used when selecting the rates for the polar codes. Many conventional approaches that use MLC with polar codes use polarization parameters optimized with a binary input alphabet for a simple channel (such as a binary erasure channel). In accordance with this disclosure, for higher-order modulation in an AWGN channel, different polarization parameters can be used for different channels that are “seen” by the different bit levels.

Once the rate of each polar code is identified, data is transmitted over at least one wireless or other channel as symbols created using the polar code(s). At a receiver, a decoder can be applied at each bit level, such as by using successive cancellation (SC) decoders starting with the least significant bit (LSB).

Various benefits can be obtained using this approach, although the specific benefits depend on the particular implementation. For example, binary alphabet polar codes can allow for the use of low-complexity encoding and decoding techniques, which can substantially reduce the complexity of the overall multilevel coding technique. Also, the use of polar codes can provide large performance improvements when used with multilevel coding techniques compared to approaches that use a single level of coding. When the code rates for all bit channels are optimized, MLC provides better performance than a single binary input alphabet mapped to a higher-order modulation. In addition, it has been shown that polar codes do not have an error floor, which means they can be used in various applications that require higher-order modulations and very low error performance. Note that these benefits are unique because they can be obtained using one or more AWGN channels, while many conventional approaches that use MLC with polar codes derive results for binary erasure channels only.

Additional details regarding the use of MLC with binary alphabet polar codes are provided below. In the discussion below, two general schemes are described as being used to support MLC with binary alphabet polar codes. In a first MLC scheme (such as is shown in FIGS. 2 through 5), each binary polar code corresponds to one bit in a bit-to-symbol mapping for each of the in-phase (I) and quadrature (Q) directions. In a second MLC scheme (such as is shown in FIGS. 6 and 7), a binary polar code corresponds to more than one bit in a bit-to-symbol mapping for each of the I and Q directions.

Although FIGS. 1A and 1B illustrate examples of systems that use MLC with binary alphabet polar codes, various changes may be made to FIGS. 1A and 1B. For example, MLC with binary alphabet polar codes could be used in any other suitable system. Moreover, infrastructure components, networks, transmitters, and receivers come in a wide variety of designs and configurations, and FIGS. 1A and 1B do not limit the scope of this disclosure to any particular infrastructure component, network, transmitter, or receiver.

FIGS. 2 through 7 illustrate example encoding and decoding schemes supporting MLC with binary alphabet polar codes in accordance with this disclosure. The encoding and decoding schemes could, for example, be used by the base stations 102-104 or by the transmitter 150 and receiver 160 to communicate over one or more wireless or other communication channels. However, the encoding and decoding schemes could be used with any other suitable devices and in any other suitable systems.

FIGS. 2 and 3 illustrate a first example implementation of a coding scheme in which each of multiple binary polar codes corresponds to one bit in each of the I and Q directions. FIG. 2 illustrates an example symbol mapping 200, which can be used with 16-QAM modulation. Each of the I and Q directions independently uses the same mapping as 4-PAM, where (b₁ b₀) denotes the bit mapping to a symbol, with b₁ and b₀ representing the most significant bit (MSB) and the least significant bit (LSB), respectively. In FIG. 2, d_(b0) represents the minimum Euclidian distance for b₀, and d_(b1) represents the minimum Euclidian distance for b₁ (assuming that the bit value for b₀ is correctly decoded and known at the receiver before making a decision for b₁). In other words, during decoding, the bit value for b₀ is determined, and the decoded bit value for b₀ is used to decode the bit value for b₁.

An encoding and decoding system 300 that supports this symbol mapping 200 is shown in FIG. 3. As shown in FIG. 3, input vectors u₁ ^(N) 302 a-302 b (each containing N bits) are respectively provided to polar encoders 304 a-304 b. The polar encoders 304 a-304 b use the input vectors 302 a-302 b and different polar codes to generate codewords x₁ ^(N) 306 a-306 b, respectively, which represent encoded vectors (each containing N bits). As described in more detail below, each polar code includes a set of frozen bits with the remaining bits being information bits. The code rate R₁ for the first polar code used by the polar encoder 304 a is expressed as K₁/N, and code rate R₂ for the second polar code used by the polar encoder 304 b is expressed as K₂/N (where K₁ and K₂ denote the number of information bits for the polar codes). The overall code rate R can be calculated as (K₁+K₂)/2N=(R₁+R₂)/2. At a given channel condition (such as a given SNR), the K₁ or K₂ value cannot be increased, which acts as a limit to the code rate for the given channel condition. In the discussion below, N_(s) denotes the number of QAM symbols that carry 2N encoded bits and can equal N/2. The codewords 306 a-306 b are provided to a symbol mapper 308, which generates a series of transmit symbols 310. Each polar encoder 304 a-304 b includes any suitable structure for generating codewords using a binary alphabet polar code. The symbol mapper 308 includes any suitable structure for mapping codewords to symbols.

The symbols 310 are transmitted over at least one communication channel 312, which suffers from noise. Each channel 312 could represent any suitable communication channel, such as a wireless or fiber optic channel. In some embodiments, each channel 312 could be estimated as an AWGN channel.

The symbols 310, as transported over the channel(s) 312 and affected by noise, are received as symbols y₁ ^(Ns) 314. LLR calculators 316 a-316 b compute LLR values for different portions of the received symbols 314 to generate blocks 318 a-318 b of LLR values. Polar decoders 320 a-320 b decode the received symbols 314 using the LLR blocks 318 a-318 b and the polar codes to generate output vectors û₁ ^(N) 322 a-322 b. Ideally, the output vectors 322 a-322 b match the input vectors 302 a-302 b. The output vectors 322 a-322 b could be provided to any suitable destination(s), such as to a common destination or to multiple destinations via de-multiplexing. Each of the polar decoders 320 a-320 b can support successive cancellation and use feedback in the form of at least some of the bits (such as the least significant bits) from one or more prior output vectors 322 a-322 b when decoding one or more current LLR blocks 318 a-318 b. Each LLR calculator 316 a-316 b includes any suitable structure for computing LLR values. Each polar decoder 320 a-320 b includes any suitable structure for generating decoded bits using LLR values and a polar code.

There are various “frozen” bits 324 a-324 b contained in the input vectors 302 a-302 b and corresponding “frozen” bits 326 a-326 b contained in the output vectors 322 a-322 b. As noted above, each frozen bit 324 a-324 b, 326 a-326 b denotes a bit whose value is fixed (either to a “1” or a “0”) in both the input vector to a polar encoder and in the output vector from a polar decoder. The remaining bits in the input vectors 302 a-302 b and the output vectors 322 a-322 b represent information bits and are used to transport data.

To support multilevel coding, the LLR calculators 316 a-316 b operate sequentially on the received symbols 314, meaning the LLR calculator 316 b (on a second bit level) generates LLR values using decoded outputs from the polar decoder 320 a (on a first bit level). For example, in response to receiving a set of symbols 314, the LLR calculator 316 a can output channel LLR blocks 318 a (such as column vectors of length N) to the polar decoder 320 a. The LLR calculator 316 b uses a new output vector û₁ ^(N) 322 a from the polar decoder 320 a to generate LLR blocks 318 b at a second bit level.

In the example shown in FIG. 3, the MLC scheme for 16-QAM employs two binary polar codes. The polar encoder 304 a and the polar decoder 320 a support a first polar code with a binary alphabet for the first bit level, with one bit (b_(0I)) in the I direction and one bit (b_(0Q)) in the Q direction. The polar encoder 304 b and the polar decoder 320 b support a second polar code with a binary alphabet for the second bit level, with one bit (b_(1I)) in the I direction and one bit (b_(1Q)) in the Q direction. Here, when decoding an i^(th) information bit, any lower decoded bits are used, meaning the second information bit is decoded using the decoded value of the first information bit, the third information bit is decoded using the decoded values of the first and second information bits, and this process can be repeated until all bits are decoded. Note, however, that other forms of decoding could be used, such as list decoding or belief-propagation decoding. Moreover, note that this approach can be easily extended to support higher-order modulation techniques. An example of this is shown in FIGS. 4 and 5, where this approach has been extended to support 64-QAM modulation.

FIGS. 4 and 5 illustrate a second example implementation of a coding scheme with three bit levels, where different bit levels may be associated with different polar coding schemes. FIG. 4 illustrates an example symbol mapping 400, which can be used with 64-QAM modulation. Each of the I and Q directions independently uses the same mapping as 8-PAM, where (b₂ b₁ b₀) denotes the bit mapping to a symbol, with b₂ and b₀ representing the MSB and LSB, respectively. In FIG. 4, d_(b0) represents the minimum Euclidian distance for b₀, d_(b1) represents the minimum Euclidian distance for b₁ (assuming that the bit value for b₀ is correctly decoded and known at the receiver before making a decision for b₁), and d_(b2) represents the minimum Euclidian distance for b₂ (assuming that the bit values for b₀ and b₁ are correctly decoded and known at the receiver before making a decision for b₂). In other words, during decoding, the bit value for b₀ is determined, the decoded bit value for b₀ is used to decode the bit value for b₁, and the decoded bit values for b₀ and b₁ are used to decode the bit value for b₂.

An encoding and decoding system 500 that supports this symbol mapping 400 is shown in FIG. 5. For higher-order modulations such as 64-QAM, one approach is to encode lower bit levels while leaving the MSB uncoded. An example of this is shown in FIG. 5, where input vectors u₁ ^(N) 502 a-502 b (each containing N bits) are respectively provided to polar encoders 504 a-504 b, while input vectors u₁ ^(N) 502 c (each containing N bits) could remain uncoded. Alternatively, the input vectors 502 c could be encoded using an encoder 504 c. The encoder 504 c could support any suitable code, such as a Bose, Chaudhuri and Hocquenghem (BCH) code to provide a certain level of error protection or a different polar code.

The polar encoders 504 a-504 b use the input vectors 502 a-502 b and different polar codes to generate codewords x₁ ^(N) 506 a-506 b, respectively. Codewords x₁ ^(N) 506 c contain either the uncoded input vectors 502 c or the outputs of the encoder 504 c. The codewords 506 a-506 c are provided to a symbol mapper 508, which generates a series of transmit symbols 510. The symbols 510 are transmitted over at least one communication channel 512, which suffers from noise.

Received symbols y₁ ^(Ns) 514 are obtained over the channel(s) 512, and LLR calculators 516 a-516 c use the received symbols 514 to generate LLR blocks 518 a-518 c. Polar decoders 520 a-520 b decode portions of the received symbols 514 using the LLR blocks 518 a-518 b and the polar codes to generate output vectors 522 a-522 b. A third decoder 520 c decodes other portions of the received symbols 514 using the LLR blocks 518 c to generate output vectors 522 c. The decoder 520 c could represent any suitable decoder, such as a maximum likelihood (ML) or other hard decoder (when the input vectors 502 c are uncoded) or a BCH, polar, or other decoder (when the input vectors 502 c are coded).

To support multilevel coding, the LLR calculators 516 a-516 c again operate sequentially on the received symbols 514. For example, in response to receiving a set of symbols 514, the LLR calculator 516 a can output channel LLR blocks 518 a (such as column vectors of length N) to the polar decoder 520 a. The LLR calculator 516 b uses a new output vector û₁ ^(N) 522 a from the polar decoder 520 a to output channel LLR blocks 518 b to the polar decoder 520 b. The LLR calculator 516 c uses the new output vectors û₁ ^(N) 522 a-522 b from the polar decoders 520 a-520 b to output channel LLR blocks 518 c to the decoder 520 c. Note again, however, that other forms of decoding could be used, such as list decoding or belief-propagation decoding.

FIGS. 6 and 7 illustrate an example implementation of a coding scheme in which one binary polar code may correspond to multiple bits for each of the I and Q directions. FIG. 6 illustrates an example symbol mapping 600, which can be used with 64-QAM modulation. Each of the I and Q directions independently uses the same Gray mapping, where (b₂ b₁ b₀) denotes the bit mapping to a symbol, with b₂ and b₀ representing the MSB and LSB, respectively. Note that the Gray mapping is applied only to the two least significant bits (b₁ and b₀) in this example, not across all eight constellation points in FIG. 6. This scheme allows large Euclidian distances for b₂ (MSB) with knowledge of correctly-decoded bits for b₁ and b₀. In this embodiment, the two least significant bits are protected with the polar code.

An encoding and decoding system 700 that supports this symbol mapping 600 is shown in FIG. 7. The encoding and decoding system 700 represents one example of a practical scheme for applying polar codes to MLC with higher-order modulation and the symbol mapping of FIG. 6. As shown in FIG. 7, input vectors 702 a-702 b are received, where the input vectors 702 a contain twice the number of bits (2N) as the input vectors 702 b (N). In the input vectors 702 a, K₁ would equal 2N minus the number of frozen bits. The input vectors 702 a are provided to a polar encoder 704 a, which uses the input vectors 702 a and a polar code to generate codewords 706 a that are mapped to the two LSBs on each of the I and Q directions (b_(0I), b_(0Q), b_(1I), and b_(1Q)).

The input vectors 702 b may remain uncoded or be subjected to coding using an encoder 704 b, such as a BCH encoder or another polar encoder with a high code rate. The uncoded or encoded input vectors 702 b represent codewords 706 b. The codewords 706 a-706 b are provided to a symbol mapper 708, which generates a series of transmit symbols 710. The symbols 710 are transmitted over at least one communication channel 712, which suffers from noise. Received symbols 714 are used by LLR calculators 716 a-716 b to generate LLR blocks 718 a (for b_(0I), b_(0Q), b_(1I) and b_(1Q)) and LLR blocks 718 b (for b_(2I) and b_(2Q)). A polar decoder 720 a decodes the LLR blocks 718 a using the polar code to generate output vectors 722 a, while a decoder 720 b (such as an ML, BCH, or polar decoder) decodes the LLR blocks 718 b into output vectors 722 b.

In the approach shown in FIG. 7, the symbols 710 can be grouped into blocks of size N_(s). For 64-QAM, each symbol uses three bits in the I direction and three bits in the Q direction. Thus, input vectors 702 a of 2N bits each are encoded using the polar encoder 704 a with the polar code, and the resulting blocks of 2N bits are multiplexed to the I and Q dimensions for the 64-QAM symbols. The third bit level positions of the I and Q dimensions for the 64-QAM symbols come from the input vectors 702 b or the outputs of the encoder 704 b, which have a length of size N. Since a Gray coding is used, the LLR values are computed according to the different mapping. Two or more bits can be decoded together at bit levels where Gray mapping is used.

Note that FIG. 7 shows the polar encoder 704 a handling the b₀ and b₁ bits and the encoder 704 b optionally handling the b₂ bits. Similarly, FIG. 7 shows the polar decoder 720 a handling the b₀ and b₁ bits and the decoder 720 b handling the b₂ bits. These bit assignments are for illustration only, and other embodiments could be used. For instance, the polar encoder 704 a could handle the b₀ bits, while the encoder 704 b handles the b₁ and b₂ bits. In those embodiments, the polar decoder 720 a would handle the b₀ bits, and the decoder 720 b would handle the b₁ and b₂ bits.

In general, with respect to any of the embodiments shown in FIGS. 2 through 7, a polar code can be characterized by a set of parameters such as (N, K, A, u_(Ac)). Here, N denotes the output block size in bits, K denotes the input information size in bits, A denotes the set of indices of the information bits (which is complemented by Ac that contains the indices of the frozen bits), and u_(Ac) denotes the values of the frozen bits. A standard generator matrix G_(N) can be used for the encoding, such as: G_(N)=B_(N)

  (1) where B_(N) is a bit reversal-based permutation matrix, and

denotes the Kronecker product of

$G_{2} = {\begin{bmatrix} 1 & 0 \\ 1 & 1 \end{bmatrix}.}$ The polar code can have a length of N=2^(n), with K denoting the dimension of the set of information bits |A|. With the generator matrix defined in Equation (1), the encoding can be described by: x₁ ^(N)=u₁ ^(N)G_(N)  (2) where u₁ ^(N) is a row vector of length N of uncoded bits, and x₁ ^(N) denotes a codeword (encoded bits) of length N. The code rate can be given by the ratio of K/N, while the set of frozen bits and their value are denoted by the vector u_(Ac) of length N-K.

There are various challenges encountered in the construction of polar codes, such as when higher-order modulation symbols are sent over an AWGN channel. When M-QAM symbols are used, this can be described as: y _(k) =s _(k) +n _(k) , k=1,2, . . . ,N _(s)  (3) where s_(k) denotes the k^(th) M-QAM symbol sent over the physical channel, n_(k) denotes the complex AWGN CN(0,σ²) with zero mean and σ² variance, and N_(s) denotes the number of symbols to transmit a code block.

By using a specially-designed symbol mapping rule (such as one shown in FIG. 2, 4, or 6), due to different Euclidean distances between symbols with 0 or 1 on bit levels from the bit-to-symbol mapping, different polar codes have different properties. For example, the second bit level is better protected than the first bit level, so the effective SNR on the first bit level is lower than the SNR on the second bit level. As a result, the code rate R₁=K₁/N (where K₁ is the number of information bits for the polar code on the first bit level and N is the code block length) is desired to be smaller than the code rate R₂=K₂/N of the polar code applied to the second bit level (where K₂ is the number of information bits for the polar code on the second bit level). One challenge in designing such polar codes involves choosing the appropriate code rates such that the error rates of the polar codes at different bit levels are similar or equal (such as within a threshold amount of one another).

The following represents an example technique for optimizing the code rates for the polar codes at different bit levels, although other techniques could be used. In one technique, rather than using the typical construction process of running Monte Carlo simulations to obtain polarization parameters for each SNR evaluation, one ordered set of equivalent channel indexes W_(N) ^((i))(u_(i)|y₁ ^(N),û₁ ^(i−1)) can be used, where the ordered set is obtained from the SNR value affecting each bit level. The W_(N) ^((i))(u_(i)|y₁ ^(N),û₁ ^(i−1)) notation used for the equivalent channel indexes above is described in Arikan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels,” IEEE Transactions on Information Theory, vol. 55, pp. 3051-3073, July 2009. For example, this can be done by analyzing the tail threshold value of probability density functions of vectors containing modified log likelihood ratios mLLR(W_(N) ^((i))), which can be defined as:

$\begin{matrix} {{{mL}\; L\;{R\left( W_{N}^{(i)} \right)}} = \left\{ \begin{matrix} {{+ {{L\; L\;{R\left( W_{N}^{(i)} \right)}}}},} & {{if}\mspace{14mu}{correct}\mspace{14mu}{decision}\mspace{14mu}{was}\mspace{14mu}{made}} \\ {{- {{L\; L\;{R\left( W_{N}^{(i)} \right)}}}},} & {{if}\mspace{14mu}{wrong}\mspace{14mu}{decision}\mspace{14mu}{was}\mspace{14mu}{made}} \end{matrix} \right.} & (4) \end{matrix}$ The log-likelihood ratio is defined as:

$\begin{matrix} {{L\; L\;{R\left( W_{N}^{(i)} \right)}} = {\log\left( \frac{W_{N}^{(i)}\left( {Y_{1}^{N},{{U_{1}^{i - 1}❘U_{i}} = 0}} \right)}{W_{N}^{(i)}\left( {Y_{1}^{N},{{U_{1}^{i - 1}❘U_{i}} = 1}} \right)} \right)}} & (5) \end{matrix}$

For a given channel SNR, a BER estimation can be determined using the mLLR values as follows. First, from a large set of mLLR data for binary modulation channels (such as data obtained from simulation), calculate a threshold τ^((i))(β) for a target probability of error β. For instance, denoting the distribution of mLLR data as f^((i))(x), the threshold τ^((i))(β) can be calculated as:

$\begin{matrix} {{\int_{\infty}^{\tau^{(i)}{(\beta)}}{{f^{(i)}(x)}d\; x}} = \beta} & (6) \end{matrix}$ In other embodiments, the mean and variance of the mLLR values can be calculated, and a Gaussian probability density function (PDF) can be constructed with the same mean and variance. This can be done using only second-order statistic information (mean and variance). Second, the effective channel is selected that has τ^((i))(β)<0, and its code rate can be expressed as:

$\begin{matrix} {R = {1 - {\frac{1}{N}{\sum\limits_{i = 1}^{N}{I\left\{ {{\tau^{(i)}(\beta)} > 0} \right\}}}}}} & (7) \end{matrix}$ where the indicator function I{τ^((i))(β)>0} equals one when τ^((i))(β)>0 and zero otherwise. This approach can be used to identify the optimal code rate for MLC by selecting the individual bit levels' code rates so that the error rates of the bit levels are approximately equal. An example of this can be expressed as: P _(b) ⁽¹⁾ ≈P _(b) ⁽²⁾ ≈ . . . ≈P _(b) ^((q))≈constant target error rate(β_(target))  (8) where P_(b) ^((i)) is the bit error rate for the i^(th) level in the q-level MLC.

In particular embodiments, the following procedure can be used to select the polar codes for use in an MLC scheme. In the following, a rate design rule is based on keeping substantially the same frame error rate (PER) for each bit level. The set of frozen bits (equivalent to choosing the coding rate R) is selected for each polar code so that substantially the same PER is achieved at the effective SNR experienced at each bit level, which can be determined by the corresponding Euclidean distance of neighboring constellation points in the symbol mapping that is being used.

A receiver (such as the receiver 160 in FIG. 1B) can use a multistage decoding strategy, which could be viewed as a higher-level extension of the successive cancellation algorithm where there is progressive decoding of bit levels rather than individual bits. At the decoder, the bits at the first bit level (in both I and Q directions) are decoded first. These decoded bits are used to remove constellation points that have different bit assignments before computing the input LLRs for the bits of the second bit level, and the same process can be repeated with the higher bit levels. This increases the effective SNR at each bit level. The design of MLC polar coding in this approach involves two main operations, namely (i) identifying the code rate at each bit level and (ii) designing polar codes with different rates for a given operating SNR point (which is equivalent to choosing the set of frozen bits).

Consider an MLC configuration with a 2^(2q)-ary digital modulation scheme. Let {K_(j): j=0, . . . , q−1} denote the set of information bits at each bit level, which gives the set of code rates {R_(j): j=0, . . . , q−1} of the binary input alphabet polar codes of length N used at each bit level. Note that coding across the I and Q axes is symmetric. Let P_(f) ^((j))(γ) denote the probability of a frame error at the j^(th) bit level (where j=0 for the LSB) at a channel SNR of γ dB. If a specially-designed symbol mapping rule (such as in FIG. 2, 4, or 6) is used, the minimum distance between adjacent constellation points is doubled with increased bit levels (assuming all bits at the previous bit level are decoded correctly). For the embodiments in FIGS. 2 through 5, this could be viewed as increasing the effective SNR at each bit level by 6 dB such that the effective SNR γ_(j) at the j^(th) bit level is: γ_(j)(dB)=γ+6j  (9) For the embodiments in FIGS. 6 and 7, this can be expressed as: γ₂(dB)=γ₁+12  (10)

The set of code rates {R_(j)} can be chosen such that the same FER P_(f) ^((j)) (γ_(j)) of the corresponding polar code is obtained (or at least in the same range) among all bit levels, which can be expressed as: P _(f) ^((j))(γ_(j))≈ P _(F) , j=0, . . . ,q−1  (11) where q is the number of bit levels per I/Q direction and P _(F) is the target FER that is minimized for the operating SNR. As an example, for 64-QAM, 8-PAM is used for both the I and Q components of the signal, and q=3. For the first bit level, the binary mapping of 8-PAM is defined by b_(0I) and b_(0Q) for the I and Q components, respectively. The rate design rule defined above states that, for a specific FER of the overall system, imposing substantially the same P_(f) ^((j)) for each bit level's polar code induces different rates R_(j) because of the different SNR γ_(j) experienced by each bit level j. The overall code design problem is therefore reduced to the design of multiple polar codes at different SNRs, and the procedure described below can be used to design the polar codes.

A successive cancellation decoder can be used to decode the polar code at each bit level. Therefore, using the procedure from above, it is straightforward to show that the overall frame error rate P_(F)(γ) for the MLC configuration is:

$\begin{matrix} {{P_{F}(\gamma)} \approx {\sum\limits_{j = 0}^{q - 1}{P_{j}^{(j)}\left( {\gamma + {6j}} \right)}}} & (12) \end{matrix}$ Solving Equation (12) for the different code rates uses an explicit relation between the code rate and the frame error rate at all SNR values, which may not be available in general. Therefore, a pragmatic approach can be used that exploits the fact that the performance is in general characterized by the weakest P_(f) ^((j)). Therefore, to maximize the MLC efficiency for a given target for P_(F)(γ), the code rates for the various bit levels can be selected such that: P _(f) ⁽⁰⁾(γ)≈P _(f) ⁽¹⁾(γ+6)≈P _(f) ⁽²⁾(γ+12)≈  (13) In this case, the target frame error rate for each bit level is P_(F)(γ)/q, and the code rates are chosen according to the effective SNR for each bit level.

By identifying the operating SNR and FER of each bit level j, the rate R_(j) and the corresponding set of unfrozen bits can be determined as follows. With this design, the low complexity of the encoder and decoder of binary input alphabet polar codes is maintained while increasing spectral efficiency through sending M-QAM symbols over a channel. A polar code can be designed for a given operating SNR and FER point using the mLLR values from Equation (4). Using, for example, Monte Carlo simulations, the first two moments of the mLLR values (the mean m, and the standard deviation σ_(i)) can be determined. An SC decoder with a random set of information bits can be used for which, at each equivalent bit channel, all previously decoded bits are assumed to be known. Note that the use of an SC decoder is optional and that other decoder realizations could be used, such as a list decoder or a belief-propagation decoder. Furthermore, the assumption that a channel is an AWGN channel is for illustration only, and other channel types could be used. If the PDF of the mLLR values is known, the probability of error of the equivalent bit channels can be directly evaluated. For example, the Gaussian approximation of a PDF can be calculated using the first two moments. This approximation is adequately accurate for highly-positive polarized equivalent bit channels. With a Gaussian approximation, the probability of bit error at the i^(th) equivalent bit channel (assuming all other previous bits are decoded properly) can be expressed as:

$\begin{matrix} {{\beta_{i} = {Q\left( {m_{i}/\sigma_{i}} \right)}}{{where}\text{:}}} & (14) \\ {{Q(x)}\overset{\Delta}{=}{\frac{1}{\sqrt{2\pi}}{\int_{x}^{\infty}{\exp\left( {{- x^{2}}/2} \right)}}}} & (15) \end{matrix}$ After computing β_(i) for all input bit locations, the indices of the information bits A are chosen to correspond to the equivalent bits with the smallest values of {β_(i)}. The frame error probability P_(F) can then be calculated as:

$\begin{matrix} {P_{F} = {{1 - {\prod\limits_{i \in A}\left( {1 - \beta_{i}} \right)}} \approx {\sum\limits_{i \in A}\beta_{i}}}} & (16) \end{matrix}$ In general, {β_(i)} are functions of the channel SNR γ, but their order tends to be insensitive to small changes in the SNR as the SNR increases. This can be important in practical communication systems since the operating region (the waterfall region of the SNR/BER curve) for a given code rate is typically within 1-2 dB and it may be necessary to have consistent ordering for that range.

Thus, for example, in a practical communication system that uses adaptive modulation, a single list can be stored that contains the universal ordering of the equivalent bit channels within a certain SNR range. A distinct list can be used for each modulation order. In each list, the indices of the bits at the top of the list can be assigned as frozen bits. The number of frozen bits (which corresponds to the code rate) can be determined by the SNR. This arrangement significantly simplifies the mechanism of designing the modulation and coding scheme (MCS) of a system. The above design procedure could be combined with any modulation scheme, where the modulation and the corresponding LLR calculation of the individual bits within each symbol are considered part of the underlying channel. With the above parameterization, the code rate |A|/N for a frame error rate P _(F) could be computed analytically. For a given P _(F), the maximum code rate can correspond to a value calculated as follows:

$\begin{matrix} {{\max{A}\mspace{14mu}{such}\mspace{14mu}{that}\mspace{14mu}{\sum\limits_{i \in A}\beta_{i}}} \leq {\overset{\_}{P}}_{F}} & (17) \end{matrix}$ where it is assumed that the indices in A are sorted in ascending order of β_(i).

One advantage of the proposed solution described above is the use of “true” polarization parameters for choosing the sets of frozen bits and information bits. This can be particularly useful, for example, when more than one communication channel is used for physical transmission. One limiting constraint of conventional polar codes is that the same physical channel is to be used for each equivalent bit channel. However, two or more channels can still provide polarization to the equivalent channels when the initial G₂ matrix is used as the base for the generator matrix. This means that the equivalent channels with the highest polarization levels can be used for transmitting the information bits, instead of some mismatched sets that are optimized for different system properties.

Note that the symbol mapping rules (such as the ones shown in FIGS. 2, 4, and 6) can introduce a desired property, such as increasing minimum Euclidian distance when moving to higher bit-levels. Gray mapping-based symbol mappings typical do not give such a desired property.

The components shown in FIGS. 3, 5, and 7 could be implemented in any suitable manner. For example, the components shown in FIGS. 3, 5, and 7 could be implemented using only hardware components or a combination of hardware and software/firmware instructions. As particular examples, the components shown in FIGS. 3, 5, and 7 could be implemented using one or more FPGAs, ASICs, or other hardware-only components. The components shown in FIGS. 3, 5, and 7 could also be implemented using one or more processing devices that execute software/firmware instructions for performing the described functions. A combination of approaches could also be used, such as when some components are implemented using only hardware and other components are implemented using one or more processing devices that execute software/firmware instructions.

Although FIGS. 2 through 7 illustrate examples of encoding and decoding schemes supporting MLC with binary alphabet polar codes, various changes may be made to FIGS. 2 through 7. For example, this disclosure is not limited to the use of two polar codes at two bit levels of an MLC scheme. Two or more binary alphabet polar codes can be used at two or more bit levels of an MLC scheme.

FIGS. 8A and 8B illustrate example methods for using MLC with binary alphabet polar codes in accordance with this disclosure. In particular, FIG. 8A illustrates an example method 800 that could be used by an encoder supporting MLC, and FIG. 8B illustrates an example method 850 that could be used by a decoder supporting MLC. These methods 800 and 850 could, for example, be used by the base stations 102-104 or by the transmitter 150 and receiver 160 to communicate over one or more wireless or other communication channels. However, the methods 800 and 850 could be used with any other suitable devices and in any other suitable systems.

As shown in FIG. 8A, data bits to be transmitted are received at step 802. This could include, for example, receiving one or more input vectors 302 a-302 b, 502 a-502 c, 702 a-702 b containing data bits to be transmitted. One or more polar codes are applied to one or more subsets of the bits to generate codewords at step 804. This could include, for example, the polar encoders 304 a-304 b, 504 a-504 b applying different polar codes to different input vectors 302 a-302 b, 502 a-502 b. This could also include the polar encoder 704 a applying a polar code to the input vectors 702 a. Note that some bits, such as most significant bits, may or may not be encoded during the generation of the codewords.

Symbols are generated using the codewords at step 806. This could include, for example, the symbol mapper 308, 508, 708 mapping the codewords to different QAM symbols based on an appropriate symbol mapping, such as the symbol mapping 200, 400, or 600. The symbols are transmitted over one or more communication channels at step 808. This could include, for example, transmitting the symbols over one or more AWGN channels.

As shown in FIG. 8B, symbols transmitted over one or more communication channels are received at step 852. This could include, for example, receiving the symbols over one or more AWGN channels. Different sets of decoding information are extracted from the received symbols at step 854. This could include, for example, the LLR calculators 316 a-316 b, 516 a-516 c, 716 a-716 b identifying LLR values using the received symbols. The LLR calculators can operate sequentially such that the LLR calculator on one bit level generates LLR values using decoded outputs from the decoder on at least one earlier bit level.

One or more polar codes are applied to one or more of the different sets of decoding information to generate decoded bits at step 856. This could include, for example, the polar decoders 320 a-320 b, 520 a-520 b applying different polar codes to different LLR blocks 318 a-318 b, 518 a-518 b at different bit levels. This could also include the polar decoder 720 a applying a polar code to the LLR blocks 718 a. In either case, the coding rate(s) of the polar code(s) allow(s) the different bit levels to have substantially similar error rates. Note that some bits (such as most significant bits at an additional bit level) could be decoded in other ways (such as by using an ML or BCH decoder). The decoded data bits at the bit different bit levels are output at step 858.

Although FIGS. 8A and 8B illustrate examples of methods for using MLC with binary alphabet polar codes, various changes may be made to FIGS. 8A and 8B. For example, while shown as a series of steps, various steps in each figure could overlap, occur in parallel, or occur any number of times.

FIG. 9 illustrates an example method 900 for designing an MLC coding scheme with binary alphabet polar codes in accordance with this disclosure. The method 900 could, for example, be performed offline one or more times prior to creating an encoding or decoding design.

As shown in FIG. 9, a target error rate is identified at step 902. This could include, for example, identifying a desired target FER for communications. The desired target PER could be based on the specific application or any other suitable criteria. An effective SNR at each of multiple bit levels associated with a particular symbol mapping rule is identified at step 904. As noted above, the symbol mapping rule may be designed to have a property that provides increased Euclidian distance as one goes to higher bit levels in MLC with knowledge of correctly-decoded bits for earlier bit level(s). For example, as noted above, the symbol mappings could provide a known increase to the effective SNR at each bit level, such as by 6 dB or 12 dB.

The code rate at each bit level is determined using the target error rate and the SNR at that bit level at step 906, and the polar codes are designed with the identified code rates at step 908. This could include, for example, selecting the code rates as described above so that the overall error rate of each polar code is substantially equivalent. This could also include using the mLLR values from Equation (4), determining their mean m_(i) and standard deviation σ_(i), constructing Gaussian PDFs using these values, estimating error rates using the PDFs, and selecting the bit locations with the worst error rates as the frozen bits.

Although FIG. 9 illustrates one example of a method 900 for designing an MLC coding scheme with binary alphabet polar codes, various changes may be made to FIG. 9. For example, while shown as a series of steps, various steps in FIG. 9 could overlap, occur in parallel, occur in a different order, or occur any number of times. Also, note that while multiple polar codes are designed in FIG. 9, a single polar code could be designed, such as for use in the system 700 of FIG. 7.

FIG. 10 illustrates an example device 1000 supporting the design of an MLC coding scheme with binary alphabet polar codes in accordance with this disclosure. The device 1000 could, for example, be used to implement the method 900 shown in FIG. 9 in order to design an MLC coding scheme with binary alphabet polar codes. Note, however, that the method 900 could be performed using other devices.

As shown in FIG. 10, the device 1000 includes a bus system 1002. The bus system 1002 is configured to support communication between at least one processing device 1004, at least one storage device 1006, at least one communications unit 1008, and at least one input/output (I/O) unit 1010.

The processing device 1004 is configured to execute instructions that can be loaded into a memory 1012. The device 1000 can include any suitable number(s) and type(s) of processing devices 1004 in any suitable arrangement. Example processing devices 1004 can include microprocessors, microcontrollers, digital signal processors, field programmable gate arrays, application specific integrated circuits, and discrete circuitry. The processing device(s) 1004 can be configured to execute processes and programs resident in the memory 1012.

The memory 1012 and a persistent storage 1014 can represent any structure(s) capable of storing and facilitating retrieval of information (such as data, program code, or other suitable information on a temporary or permanent basis). The memory 1012 can represent a random access memory or any other suitable volatile or non-volatile storage device(s). The persistent storage 1014 can contain one or more components or devices supporting longer-term storage of data, such as a read-only memory, hard drive, Flash memory, or optical disc.

The communications unit 1008 is configured to support communications with other systems or devices. For example, the communications unit 1008 can include a network interface card or a wireless transceiver facilitating communications over a network. The communications unit 1008 can be configured to support communications through any suitable physical or wireless communication link(s).

The I/O unit 1010 is configured to allow for input and output of data. For example, the I/O unit 1010 can be configured to provide a connection for user input through a keyboard, mouse, keypad, touchscreen, or other suitable input device. The I/O unit 1010 can also be configured to send output to a display, printer, or other suitable output device.

Although FIG. 10 illustrates one example of a device 1000 supporting the design of an MLC coding scheme with binary alphabet polar codes, various changes may be made to FIG. 10. For example, various components in FIG. 10 could be combined, further subdivided, or omitted and additional components could be added according to particular needs. In general, computing devices can come in a wide variety of configurations, from servers to desktop or laptop computers to portable devices such as mobile smartphones. FIG. 10 does not limit this disclosure to any particular computing device.

In some embodiments, various functions described in this patent document are implemented or supported by a computer program that is formed from computer readable program code and that is embodied in a computer readable medium. The phrase “computer readable program code” includes any type of computer code, including source code, object code, and executable code. The phrase “computer readable medium” includes any type of medium capable of being accessed by a computer, such as read only memory (ROM), random access memory (RAM), a hard disk drive, a compact disc (CD), a digital video disc (DVD), or any other type of memory. A “non-transitory” computer readable medium excludes wired, wireless, optical, or other communication links that transport transitory electrical or other signals. A non-transitory computer readable medium includes media where data can be permanently stored and media where data can be stored and later overwritten, such as a rewritable optical disc or an erasable memory device.

It may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms “application” and “program” refer to one or more computer programs, software components, sets of instructions, procedures, functions, objects, classes, instances, related data, or a portion thereof adapted for implementation in a suitable computer code (including source code, object code, or executable code). The terms “transmit,” “receive,” and “communicate,” as well as derivatives thereof, encompasses both direct and indirect communication. The terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The term “or” is inclusive, meaning and/or. The phrase “associated with,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, have a relationship to or with, or the like. The phrase “at least one of,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be needed. For example, “at least one of: A, B, and C” includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C.

While this disclosure has described certain embodiments and generally associated methods, alterations and permutations of these embodiments and methods will be apparent to those skilled in the art. Accordingly, the above description of example embodiments does not define or constrain this disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this disclosure, as defined by the following claims. 

What is claimed is:
 1. A method comprising: receiving multiple bits to be transmitted; applying a first polar code to a first subset of the multiple bits to generate first encoded bits, the first encoded bits associated with a first bit level of a multilevel coding scheme; generating one or more symbols using the first encoded bits and bits associated with a second bit level of the multilevel coding scheme; and wherein the first polar code is associated with a first coding rate.
 2. The method of claim 1, further comprising: applying a second polar code to a second subset of the multiple bits to generate second encoded bits, the second encoded bits associated with the second bit level of the multilevel coding scheme.
 3. The method of claim 2, wherein the second polar code is associated with a second coding rate such that the first and second bit levels have substantially equal error rates.
 4. The method of claim 1, wherein: the first bit level represents one or more least significant bits of the one or more symbols; and the second bit level represents one or more other bits of the one or more symbols.
 5. The method of claim 1, wherein the first polar code corresponds to one bit in a bit-to-symbol mapping for an in-phase (I) direction and one bit in the bit-to-symbol mapping for a quadrature (Q) direction.
 6. The method of claim 1, wherein the first polar code corresponds to multiple bits in a bit-to-symbol mapping for an in-phase (I) direction and multiple bits in the bit-to-symbol mapping for a quadrature (Q) direction.
 7. A method comprising: receiving multiple bits to be transmitted; applying a first polar code to a first subset of the multiple bits to generate first encoded bits, the first encoded bits associated with a first bit level of a multilevel coding scheme; generating one or more symbols using the first encoded bits and bits associated with a second bit level of the multilevel coding scheme, wherein generating the one or more symbols comprises using a symbol mapping of bits to symbols, the symbol mapping providing an increasing Euclidian distance between symbols having a common value at a specific bit position as the bit level increases assuming each bit at each lower bit level is decoded correctly; and wherein the first binary alphabet polar code is associated with a first coding rate.
 8. An apparatus comprising: a first encoder configured to (i) receive multiple bits to be transmitted and (ii) apply a first polar code to a first subset of the multiple bits to generate first encoded bits, the first encoded bits associated with a first bit level of a multilevel coding scheme; a symbol generator configured to map the first encoded bits and bits associated with a second bit level of the multilevel coding scheme to one or more symbols for transmission; and wherein the first polar code is associated with a first coding rate.
 9. The apparatus of claim 8, further comprising: a second encoder configured to apply a second polar code to a second subset of the multiple bits to generate second encoded bits, the second encoded bits associated with the second bit level of the multilevel coding scheme.
 10. The apparatus of claim 9, wherein the second polar code is associated with a second coding rate such that the first and second bit levels have substantially equal error rates.
 11. The apparatus of claim 8, wherein: the first bit level represents one or more least significant bits of the one or more symbols; and the second bit level represents one or more other bits of the one or more symbols.
 12. The apparatus of claim 8, wherein the first polar code corresponds to one bit in a bit-to-symbol mapping for an in-phase (I) direction and one bit in the bit-to-symbol mapping for a quadrature (Q) direction.
 13. The apparatus of claim 8, wherein the first polar code corresponds to multiple bits in a bit-to-symbol mapping for an in-phase (I) direction and multiple bits in the bit-to-symbol mapping for a quadrature (Q) direction.
 14. An apparatus comprising: a first encoder configured to (i) receive multiple bits to be transmitted and (ii) apply a first polar code to a first subset of the multiple bits to generate first encoded bits, the first encoded bits associated with a first bit level of a multilevel coding scheme; a symbol generator configured to map the first encoded bits and bits associated with a second bit level of the multilevel coding scheme to one or more symbols for transmission, wherein the symbol generator is configured to use a symbol mapping of bits to symbols, the symbol mapping providing an increasing Euclidian distance between symbols having a common value at a specific bit position as the bit level increases assuming each bit at each lower bit level is decoded correctly; and wherein the first polar code is associated with a first coding rate.
 15. A method comprising: applying a first polar code to first decoding information associated with one or more symbols to generate first decoded bits, the first decoding information associated with a first bit level of a multilevel coding scheme; outputting the first decoded bits and bits associated with a second bit level of the multilevel coding scheme; and wherein the first polar code is associated with a first coding rate.
 16. The method of claim 15, further comprising: applying a second polar code to second decoding information associated with the one or more symbols to generate second decoded bits, the second decoded bits associated with the second bit level.
 17. The method of claim 16, wherein the second polar code is associated with a second coding rate such that the first and second bit levels have substantially equal error rates.
 18. The method of claim 17, further comprising: calculating log-likelihood ratio (LLR) values associated with the bit levels using the one or more symbols to generate the first and second decoding information; wherein the LLR values associated with the second bit level are calculated using the first decoded bits.
 19. The method of claim 16, further comprising: applying a third decoding scheme to third decoding information associated with the one or more symbols to generate third decoded bits, the third decoding information associated with a third bit level.
 20. An apparatus comprising: a first decoder configured to apply a first polar code to first decoding information associated with one or more symbols to generate first decoded bits, the first decoding information associated with a first bit level of a multilevel coding scheme, the multilevel coding scheme having a second bit level; and wherein the first polar code is associated with a first coding rate.
 21. The apparatus of claim 20, further comprising: a second decoder configured to apply a second polar code to second decoding information associated with the one or more symbols to generate second decoded bits, the second decoded bits associated with the second bit level.
 22. The apparatus of claim 21, wherein the second polar code is associated with a second coding rate such that the first and second bit levels have substantially equal error rates.
 23. The apparatus of claim 21, further comprising: log-likelihood ratio (LLR) calculators configured to calculate log-likelihood ratio (LLR) values associated with the bit levels using the one or more symbols to generate the first and second decoding information; and wherein the LLR values for the second bit level are calculated using the first decoded bits.
 24. The apparatus of claim 21, further comprising: a third decoder configured to apply a third decoding scheme to third decoding information associated with the one or more symbols to generate third decoded bits, the third decoding information associated with a third bit level.
 25. The apparatus of claim 20, wherein the first decoder comprises one of: a successive cancellation decoder, a list decoder, and a belief-propagation decoder.
 26. The method of claim 1, wherein the first polar code is a binary alphabet polar code.
 27. The method of claim 2, wherein the second polar code is a binary alphabet polar code.
 28. The apparatus of claim 8, wherein the first polar code is a binary alphabet polar code.
 29. The apparatus of claim 9, wherein the second polar code is a binary alphabet polar code.
 30. The method of claim 15, wherein the first polar code is a binary alphabet polar code.
 31. The method of claim 16, wherein the second polar code is a binary alphabet polar code.
 32. The apparatus of claim 20, wherein the first polar code is a binary alphabet polar code.
 33. The apparatus of claim 21, wherein the second polar code is a binary alphabet polar code. 